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| $XJXVW $GYDQFHG ,QIRUPDWLRQ $6/9 9 0 i 0 i &026 )ODVK ((3520 )HDWXUHV * Organization: 2Mx8 / 1Mx16 * Sector architecture - One 16K; two 8K; one 32K; and thirty-one 64K byte sectors - One 8K; two 4K; one 16K; and thirty-one 32K word sectors - Boot code sector architecture--T (top) or B (bottom) - Erase any combination of sectors or full chip * Single 2.7-3.6V power supply for read/write operations * Sector protection * High speed 70/80/90/120 ns address access time * Automated on-chip programming algorithm - Automatically programs/verifies data at specified address * Automated on-chip erase algorithm - Automatically preprograms/erases chip or specified sectors * Hardware RESET pin - Resets internal state machine to read mode * Low power consumption - 200 nA typical automatic sleep mode current - 200 nA typical standby current - 10 mA typical read current * JEDEC standard software, packages and pinouts - 48-pin TSOP - 44-pin SO (availability TBD) * CFI (Common Flash Interface) compliant * Detection of program/erase cycle completion - DQ7 DATA polling - DQ6 toggle bit - RY/BY output * Erase suspend/resume - Supports reading data from or programming data to a sector not being erased * Low VCC write lock-out below 1.5V * 10 year data retention at 150C * 100,000 write/erase cycle endurance /RJLF EORFN GLDJUDP RY/BY VCC VSS RESET Program/erase control Command register CE OE Program voltage generator Chip enable Output enable Logic STB Data latch Sector protect/ erase voltage switches Erase voltage generator DQ0-DQ15 (A-1) 3LQ DUUDQJHPHQW 48-pin TSOP A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE RESET NC NC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 44-pin SO Reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 WE A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC Input/output buffers WE BYTE $6/9 VCC detector Timer Address latch STB Y decoder Y gating X decoder Cell matrix A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 A0-A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 6HOHFWLRQ JXLGH 29LV160-70 Maximum access time Maximum chip enable access time Maximum output enable access time tAA tCE tOE 70 70 30 29LV160-80 80 80 30 29LV160-90 90 90 35 29LV160-120 120 120 50 Unit ns ns ns 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 1 of 29 &RS\ULJKW $OOLDQFH 6HPLFRQGXFWRU $OO ULJKWV UHVHUYHG $6/9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 $6/9 )XQFWLRQDO GHVFULSWLRQ The AS29LV160 is a 16 megabit, 3.0 volt Flash memory organized as 2 Megabyte of 8 bits/1 Megabyte of 16 bits each. For flexible erase and program capability, the 8 megabits of data is divided into thirty-five sectors: one 16K, two 8K, one 32K, and thirty-one 64k byte sectors; or one 8K, two 4K, one 16K, and thirty-one 32K word sectors. The x8 data appears on DQ0-DQ7; the x16 data appears on DQ0-DQ15. The AS29LV160 is offered in JEDEC standard 48-pin TSOP, 48-pin BGA, and 44-pin SO (availability TBD) packages. This device is designed to be programmed and erased in-system with a single 3.0V VCC supply. The device can also be reprogrammed in standard EPROM programmers. The AS29LV160 offers access times of 70/80/90/120 ns, allowing 0-wait state operation of high speed microprocessors. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls. Word mode (x16 output) is selected by BYTE = high. Byte mode (x8 output) is selected by BYTE = low. The AS29LV160 is fully compatible with the JEDEC single power supply Flash standard. Write commands are sent to the command register using standard microprocessor write timings. An internal state-machine uses register contents to control the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Read data from the device occurs in the same manner as other Flash or EPROM devices. Use the program command sequence to invoke the automated on-chip programming algorithm that automatically times the program pulse widths and verifies proper cell margin. Use the erase command sequence to invoke the automated on-chip erase algorithm that preprograms the sector (if it is not already programmed before executing the erase operation), times the erase pulse widths, and verifies proper cell margin. Boot sector architecture enables the system to boot from either the top (AS29LV160T) or the bottom (AS29LV160B) sector. Sector erase architecture allows specified sectors of memory to be erased and reprogrammed without altering data in other sectors. A sector typically erases and verifies within 1.0 seconds. Hardware sector protection disables both program and erase operations in all, or any combination of, the nineteen sectors. The device provides true background erase with Erase Suspend, which puts erase operations on hold to either read data from, or program data to, a sector that is not being erased. The chip erase command will automatically erase all unprotected sectors. A factory shipped AS29LV160 is fully erased (all bits = 1). The programming operation sets bits to 0. Data is programmed into the array one byte at a time in any sequence and across sector boundaries. A sector must be erased to change bits from 0 to 1. Erase returns all bytes in a sector to the erased state (all bits = 1). Each sector is erased individually with no effect on other sectors. The device features single 3.0V power supply operation for Read, Write, and Erase functions. Internally generated and regulated voltages are provided for the Program and Erase operations. A low VCC detector automatically inhibits write operations during power transtitions. The RY/BY pin, DATA polling of DQ7, or toggle bit (DQ6) may be used to detect end of program or erase operations. The device automatically resets to the read mode after program/erase operations are completed. DQ2 indicates which sectors are being erased. The AS29LV160 resists accidental erasure or spurious programming signals resulting from power transitions. Control register architecture permits alteration of memory contents only after successful completion of specific command sequences. During power up, the device is set to read mode with all program/erase commands disabled when VCC is less than VLKO (lockout voltage). The command registers are not affected by noise pulses of less than 5 ns on OE, CE, or WE. To initiate write commands, CE and WE must be logical zero and OE a logical 1. When the device's hardware RESET pin is driven low, any program/erase operation in progress is terminated and the internal state machine is reset to read mode. If the RESET pin is tied to the system reset circuitry and a system reset occurs during an automated on-chip program/erase algorithm, data in address locations being operated on may become corrupted and requires rewriting. Resetting the device enables the system's microprocessor to read boot-up firmware from the Flash memory. The AS29LV160 uses Fowler-Nordheim tunnelling to electrically erase all bits within a sector simultaneously. Bytes are programmed one at a time using EPROM programming mechanism of hot electron injection. 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 2 of 29 $6/9 2SHUDWLQJ PRGHV Mode ID read MFR code ID read device code Read Standby Output disable Write Enable sector protect Sector unprotect Temporary sector unprotect Verify sector protect Verify sector unprotect Hardware Reset CE L L L H L L L L X L L X OE L L L X H H VID VID X L L X WE H H H X H L Pulse/L Pulse/L X H H X A0 L H A0 X X A0 L L X L L X A1 L L A1 X X A1 H H X H H X A6 L L A6 X X A6 L H X L H X A9 VID VID A9 X X A9 VID VID X VID VID X RESET H H H H H H H H VID H H L DQ Code Code DOUT High Z High Z DIN X X X Code Code High Z L = Low ( 0RGH GHILQLWLRQV Item ID MFR code, device code Read mode Description Selected by A9 = VID(9.5V-10.5V), CE = OE = A1 = A6 = L, enabling outputs. When A0 is low (VIL) the output data = 52h, a unique Mfr. code for Alliance Semiconductor Flash products. When A0 is high (VIH), DOUT represents the device code for the AS29LV160. Selected with CE = OE = L, WE = H. Data is valid in tACC time after addresses are stable, tCE after CE is low and tOE after OE is low. Selected with CE = H. Part is powered down, and ICC reduced to <1.0 A when CE = VCC 0.3V = RESET. If activated during an automated on-chip algorithm, the device completes the operation before entering standby. Part remains powered up; but outputs tri-stated with OE pulled high. Selected with CE = WE = L, OE = H. Accomplish all Flash erasure and programming through the command register. Contents of command register serve as inputs to the internal state machine. Address latching occurs on the falling edge of WE or CE, whichever occurs later. Data latching occurs on the rising edge WE or CE, whichever occurs first. Filters on WE prevent spurious noise events from appearing as write commands. Hardware protection circuitry implemented with external programming equipment causes the device to disable program and erase operations for specified sectors. For in-system sector protection, refer to Sector protect algorithm on page 15. Standby Output disable Write Enable sector protect Disables sector protection for all sectors using external programming equipment. All sectors must be Sector unprotect protected prior to sector unprotection. For in-system sector unprotection, refer to Sector unprotect algorithm on page 15. 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 3 of 29 $6/9 Item Verify sector protect/ unprotect Description Verifies write protection for sector. Sectors are protected from program/erase operations on commercial programming equipment. Determine if sector protection exists in a system by writing the ID read command sequence and reading location XXX02h, where address bits A12-18 select the defined sector addresses. A logical 1 on DQ0 indicates a protected sector; a logical 0 indicates an unprotected sector. Temporarily disables sector protection for in-system data changes to protected sectors. Apply +10V to RESET Temporary to activate temporary sector unprotect mode. During temporary sector unprotect mode, program protected sector unprotect sectors by selecting the appropriate sector address. All protected sectors revert to protected state on removal of +10V from RESET. RESET Deep power down Resets the interal state machine to read mode. If device is programming or erasing when RESET = L, data may be corrupted. Hold RESET low to enter deep power down mode (<1 A). Recovery time to start of first read cycle is 50ns. Enabled automatically when addresses remain stable for 300ns. Typical current draw is 1 A with no current Automatic sleep drawn by the external devices from teh output pin. Existing data is available to the system during this mode. mode If an address is changed, automatic sleep mode is disabled and new data is returned within standard access times. )OH[LEOH 6HFWRU $UFKLWHFWXUH Bottom boot sector architecture (AS29LV160B) Sector 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 x8 000000-003FFF 004000-005FFF 006000-007FFF 008000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF x16 00000-01FFF 02000-02FFF 03000-03FFF 04000-07FFF 08000-0FFFF 10000-17FFF 18000-1FFFF 20000-27FFF 28000-2FFFF 30000-37FFF 38000-3FFFF 40000-47FFF 48000-4FFFF 50000-57FFF 58000-5FFFF 60000-67FFF 68000-6FFFF 70000-77FFF 78000-7FFFF Size (Kbytes) 16 8 8 32 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Top boot sector architecture (AS29LV160T) x8 000000-00FFFF 010000-01FFFF 020000-02FFFF 030000-03FFFF 040000-04FFFF 050000-05FFFF 060000-06FFFF 070000-07FFFF 080000-08FFFF 090000-09FFFF 0A0000-0AFFFF 0B0000-0BFFFF 0C0000-0CFFFF 0D0000-0DFFFF 0E0000-0EFFFF 0F0000-0FFFFF 100000-10FFFF 110000-11FFFF 120000-12FFFF x16 00000-07FFF 08000-0FFFF 10000-17FFF 18000-1FFFF 20000-27FFF 28000-2FFFF 30000-37FFF 38000-3FFFF 40000-47FFF 48000-4FFFF 50000-57FFF 58000-5FFFF 60000-67FFF 68000-6FFFF 70000-77FFF 78000-7FFFF 80000-87FFF 88000-8FFFF 90000-97FFF Size (Kbytes) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 4 of 29 $6/9 Bottom boot sector architecture (AS29LV160B) Sector 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 x8 100000-10FFFF 110000-11FFFF 120000-12FFFF 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1FFFFF x16 80000-87FFF 88000-8FFFF 90000-97FFF 98000-9FFFF A0000-A7FFF A8000-AFFFF B0000-B7FFF B8000-BFFFF C0000-C7FFF C8000-CFFFF D0000-D7FFF D8000-DFFFF E0000-E7FFF E8000-EFFFF F0000-F7FFF F8000-FFFFF Size (Kbytes) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 Top boot sector architecture (AS29LV160T) x8 130000-13FFFF 140000-14FFFF 150000-15FFFF 160000-16FFFF 170000-17FFFF 180000-18FFFF 190000-19FFFF 1A0000-1AFFFF 1B0000-1BFFFF 1C0000-1CFFFF 1D0000-1DFFFF 1E0000-1EFFFF 1F0000-1F7FFF 1F8000-1F9FFF 1FA000-1FBFFF 1FC000-1FFFFF x16 98000-9FFFF A0000-A7FFF A8000-AFFFF B0000-B7FFF B8000-BFFFF C0000-C7FFF C8000-CFFFF D0000-D7FFF D8000-DFFFF E0000-E7FFF E8000-EFFFF F0000-F7FFF F8000-FBFFF FC000-FCFFF FD000-FDFFF FE000-FFFFF Size (Kbytes) 64 64 64 64 64 64 64 64 64 64 64 64 32 8 8 16 In word mode, there are one 8K word, two 4K word, one 16K word, and fifteen 32K word sectors. Address range is A19-A-1 if BYTE = VIL; address range is A19-A0 if BYTE = VIH. ,' 6HFWRU DGGUHVV WDEOH Bottom boot sector architecture Sector 0 1 2 3 4 5 6 7 8 9 10 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 (AS29LV160B) A19 A18 A17 A16 0 0 0 0 0 1 1 0 0 1 1 0 A15 0 0 0 0 1 0 1 0 1 0 1 0 A14 0 0 0 1 X X X X X X X X A13 0 1 1 X X X X X X X X X A12 X 0 1 X X X X X X X X X A19 0 0 0 0 0 0 0 0 0 0 0 0 A18 0 0 0 0 0 0 0 0 1 1 1 1 Top boot sector architecture (AS29LV160T) A17 0 0 0 0 1 1 1 1 0 0 0 0 A16 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 A14 X X X X X X X X X X X X A13 X X X X X X X X X X X X A12 X X X X X X X X X X X X 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 5 of 29 $6/9 Bottom boot sector architecture Sector 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 (AS29LV160B) 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Top boot sector architecture (AS29LV160T) 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X 0 1 1 1 X X X X X X X X X X X X X X X X X X X X 0 0 1 X X X X X X X X X X X X X X X X X X X X 0 1 X 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 6 of 29 $6/9 &RPPDQG IRUPDW ELW PRGH Bus Write Operations1 Command Length Read/Reset Auto Select Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Block Erase Erase Suspend Erase Resume CFI Query 1 3 3 4 3 1st bus cycle Address X 555 555 555 555 Data F0 AA AA AA AA 2AA 2AA 2AA 2AA 55 55 55 55 X 555 555 555 FO 90 A0 20 *2 PA *2 PD 2nd bus cycle Address Data 3rd bus cycle Address Data 4th bus cycle 5th bus cycle 6th bus cycle Address Data Address Data Address Data 2 X A0 PA PD 2 6 6 1 1 1 X 555 555 X X X 90 AA AA B0 30 98 X 2AA 2AA OO 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 BA 10 30 Key: L =Low ( 5($' FRGHV Mode MFR code (Alliance Semiconductor) x8 T boot Device code x8 B boot x16 T boot x16 B boot Sector protection Key: L =Low ( A19-A12 X 1 A6 L L L L L L A1 L L L L L H A0 L H H H H L Code 52h CAh 49h 22C4h 2249h 01h protected 00h unprotected X X X X Sector address 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 7 of 29 $6/9 &RPPDQG IRUPDW ELW PRGH Bus Write Operations1 Command Read/Reset Auto Select Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset Chip Erase Block Erase Erase Suspend Erase Resume CFI query Length 1 3 3 4 3 1st bus cycle Address X AAA AAA AAA AAA Data F0 AA AA AA AA 555 555 555 555 55 55 55 55 X AAA AAA AAA FO 90 A0 20 *2 PA * PD 2nd bus cycle Address Data 3rd bus cycle Address Data 4th bus cycle 5th bus cycle 6th bus cycle Address Data Address Data Address Data 2 X A0 PA PD 2 6 6 1 1 1 X AAA AAA X X X 90 AA AA B0 30 98 X 555 555 OO 55 55 AAA AAA 80 80 AAA AAA AA AA 555 555 55 55 AAA BA 10 30 [ 'RQW FDUH 3$ 3URJUDP DGGUHVV %$ $Q\ DGGUHVV LQ WKH EORFN 6HH IRRWQRWH RQ SUHFHHGLQJ SDJH )RXUWK EXV F\FOH LQ WKH DXWRVHOHFW PRGH LV D UHDG F\FOH ZLWK WKH GDWD LQ WKH 5($' FRGHV WDEOH RQ WKH SUFHHGLQJ SDJH H[SHFWHG 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 8 of 29 $6/9 &RPPDQG GHILQLWLRQV Item Description Initiate read or reset operations by writing the Read/Reset command sequence into the command register. This allows the microprocessor to retrieve data from the memory. Device remains in read mode until command register contents are altered. Device automatically powers up in read/reset state. This feature allows only reads, therefore ensuring no spurious memory content alterations during power up. AS29LV160 provides manufacturer and device codes in two ways. External PROM programmers typically access the device codes by driving +10V on A9. AS29LV160 also contains an ID Read command to read the device code with only +3V, since multiplexing +10V on address lines is generally undesirable. ID Read Initiate device ID read by writing the ID Read command sequence into the command register. Follow with a read sequence from address XXX00h to return MFR code. Follow ID Read command sequence with a read sequence from address XXX01h to return device code. To verify write protect status on sectors, read address XXX02h. Sector addresses A19-A12 produce a 1 on DQ0 for protected sector and a 0 for unprotected sector. Exit from ID read mode with Read/Reset command sequence. Holding RESET low for 500 ns resets the device, terminating any operation in progress; data handled in the operation is corrupted. The internal state machine resets 20 s after RESET is driven low. RY/BY remains low until internal state machine resets. After RESET is set high, there is a delay of 50 ns for the device to permit read operations. Programming the AS29LV160 is a four bus cycle operation performed on a byte-by-byte or wordby-word basis. Two unlock write cycles precede the Program Setup command and program data write cycle. Upon execution of the program command, no additional CPU controls or timings are necessary. Addresses are latched on the falling edge of CE or WE, whichever is last; data is latched on the rising edge of CE or WE, whichever is first. The AS29LV160's automated on-chip program algorithm provides adequate internally-generated programming pulses and verifies the programmed cell margin. Byte/word Programming Check programming status by sampling data on the RY/BY pin, or either the DATA polling (DQ7) or toggle bit (DQ6) at the program address location. The programming operation is complete if DQ7 returns equivalent data, if DQ6 = no toggle, or if RY/BY pin = high. The AS29LV160 ignores commands written during programming. A hardware reset occurring during programming may corrupt the data at the programmed location. AS29LV160 allows programming in any sequence, across any sector boundary. Changing data from 0 to 1 requires an erase operation. Attempting to program data 0 to 1 results in either DQ5 = 1 (exceeded programming time limits); reading this data after a read/reset operation returns a 0. When programming time limit is exceeded, DQ5 reads high, and DQ6 continues to toggle. In this state, a Reset command returns the device to read mode. Reset/Read Hardware Reset 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 9 of 29 $6/9 &RPPDQG GHILQLWLRQV Item Description The unlock bypass feature increases the speed at which the system programs bytes or words to the device because it bypasses the first two unlock cycles of the standard program command sequence. To initiate the unlock bypass command sequence, two unlock cycles must be written, then followed by a third cycle which has the unlock bypass command, 20h. Unlock Bypass Command Sequence The device then begins the unlock bypass mode. In order to program in this mode, a two cycle unlock bypass program sequence is required. The first cycle has the unlock bypass program command, A0h. It is followed by a second cycle which has the program address and data. To program additional data, the same sequence must be followed. The unlock bypass mode has two valid commands, the Unlock Bypass Program command and the Unlock Bypass Reset command. The only way the system can exit the unlock bypass mode is by issuing the unlock bypass reset command sequence. This sequence involves two cycles. The first cycle contains the data, 90h. The second cycle contains the data 00h. Addresses are don't care for both cycles. The device then returns to reading array data. Chip erase requires six bus cycles: two unlock write cycles; a setup command, two additional unlock write cycles; and finally the Chip Erase command. Chip Erase Chip erase does not require logical 0s to be written prior to erasure. When the automated on-chip erase algorithm is invoked with the Chip Erase command sequence, AS29LV160 automatically programs and verifies the entire memory array for an all-zero pattern prior to erase. The 29LV160 returns to read mode upon completion of chip erase unless DQ5 is set high as a result of exceeding time limit. Sector erase requires six bus cycles: two unlock write cycles, a setup command, two additional unlock write cycles, and finally the Sector Erase command. Identify the sector to be erased by addressing any location in the sector. The address is latched on the falling edge of WE; the command, 30h is latched on the rising edge of WE. The sector erase operation begins after a sector erase time-out. To erase multiple sectors, write the Sector Erase command to each of the addresses of sectors to erase after following the six bus cycle operation above. Timing between writes of additional sectors must be less than the erase time-out period, or the AS29LV160 ignores the command and erasure begins. During the time-out period any falling edge of WE resets the time-out. Any command (other than Sector Erase or Erase Suspend) during time-out period resets the AS29LV160 to read mode, and the device ignores the sector erase command string. Erase such ignored sectors by restarting the Sector Erase command on the ignored sectors. The entire array need not be written with 0s prior to erasure. AS29LV160 writes 0s to the entire sector prior to electrical erase; writing of 0s affects only selected sectors, leaving non-selected sectors unaffected. AS29LV160 requires no CPU control or timing signals during sector erase operations. Automatic sector erase begins after sector erase time-out from the last rising edge of WE from the sector erase command stream and ends when the DATA polling (DQ7) is logical 1. DATA polling address must be performed on addresses that fall within the sectors being erased. AS29LV160 returns to read mode after sector erase unless DQ5 is set high by exceeding the time limit. In order to achieve long term system compatibility, certain information about the internal configuration of the memory is provided which can be accessed in this mode. According to this information, system software may be configured for both upward and downward compatibility with Flash in a similar family. CFI mode can be entered by issuing CFI command either from read or from autoselect mode. The system can read CFI information at the addresses given in the tables below. Sector Erase Common Flash Interface 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 10 of 29 $6/9 &RPPDQG GHILQLWLRQV Item Description Erase Suspend allows interruption of sector erase operations to read data from or program data to a sector not being erased. Erase suspend applies only during sector erase operations, including the time-out period. Writing an Erase Suspend command during sector erase time-out results in immediate termination of the time-out period and suspension of erase operation. AS29LV160 ignores any commands during erase suspend other than Read/Reset, Program or Erase Resume commands. Writing the Erase Resume Command continues erase operations. Addresses are Don't Care when writing Erase Suspend or Erase Resume commands. AS29LV160 takes 0.2-15 s to suspend erase operations after receiving Erase Suspend command. To determine completion of erase suspend, either check DQ6 after selecting an address of a sector not being erased, or poll RY/BY. Check DQ2 in conjunction with DQ6 to determine if a sector is being erased. AS29LV160 ignores redundant writes of Erase Suspend. While in erase-suspend mode, AS29LV160 allows reading data (erase-suspend-read mode) from or programming data (erase-suspend-program mode) to any sector not undergoing sector erase; these operations are treated as standard read or standard programming mode. AS29LV160 defaults to erase-suspend-read mode while an erase operation has been suspended. Write the Resume command 30h to continue operation of sector erase. AS29LV160 ignores redundant writes of the Resume command. AS29LV160 permits multiple suspend/resume operations during sector erase. When attempting to write to a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <1 s. When attempting to erase a protected sector, DATA polling and Toggle Bit 1 (DQ6) are activated for about <5 s. In both cases, the device returns to read mode without altering the specified sectors. Erase Suspend Sector Protect 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 11 of 29 $6/9 &), GHVFULSWLRQ DQG WDEOHV &RPPRQ )ODVK 0HPRU\ ,QWHUIDFH 4XHU\ ,GHQWLILFDWLRQ 6WULQJ Addresses (Word Mode) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Addresses (Byte Mode) 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Description Query unique ASCII string (QRY) Primary OEM command set Address for primary extended table Alternate OEM command set (00h = does not exist) Address for alternate OEM extended table (00h = does not exist) 6\VWHP ,QWHUIDFH 6WULQJ Addresses (Word Mode) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Addresses (Byte Mode) 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch Data 0027h 0036h 0000h 0000h 0004h 0000h 000Ah 0000h 0005h 0000h 0004h 0000h Description VccMin.(write/erase), D7-D4:volt, D3-D0: 100 millivolt VccMax.(write/erase), D7-D4: volt, D3-D0: 100 millivolt VppMin. Voltage (00h = no Vpp pin present) VppMax. Voltage (00h = no Vpp in present) Typical timeout per single byte/word write 2N us Typical timeout for Min. size buffer write 2N us (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported) 'HYLFH *HRPHWU\ 'HILQLWLRQ Addresses (Word Mode) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h Addresses (Byte Mode) 4Eh 50h 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h Data 0015h 0002h 0000h 0000h 0000h 0004h 0000h 0000h 0040h 0000h Description Device size = 2N byte Flash device interface description Max. number of byte in multi-byte write = 2N (00h = not supported) Number of erase block regions within device Erase block region 1 information 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 12 of 29 $6/9 Addresses (Word Mode) 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Addresses (Byte Mode) 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h Data 0001h 0000h 0020h 0000h 0000h 0000h 0080h 0000h 001Eh 0000h 0000h 0001h Description Erase block region 2 information Erase block region 3 information Erase block region 4 information 3ULPDU\ 9HQGRU6SHFLILF ([WHQGHG 4XHU\ Addresses (Word Mode) 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch Addresses (Byte Mode) 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 92h 94h 96h 98h Data 0050h 0052h 0049h 0031h 0030h 0000h 0002h 0001h 0001h 0004h 0000h 0000h 0000h Description Query-unique ASCII string (PRI) Major version number, ASCII Minor version number, ASCII Address sensitive unlock, 0 = required, 1 = not required Erase suspend, 0 = not supported, 1 = to read only, 2 = to read and write Sector protect, 0 = not supported, X = number of sectors in per group Sector temporary unprotect, 00 = not supported, 01 = supported Sector protect/unprotect scheme Simultaneous operation, 00 = not supported, 01 = supported Burst mode type, 00 = not supported , 01 = supported Page mode type, 00 = not supported, 01 = 4 word page, 02 = 8 word page 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 13 of 29 $6/9 6WDWXV RSHUDWLRQV DATA polling (DQ7) Only active during automated on-chip algorithms or sector erase time outs. DQ7 reflects complement of data last written when read during the automated on-chip program algorithm (0 during erase algorithm); reflects true data when read after completion of an automated on-chip program algorithm (1 after completion of erase agorithm). Active during automated on-chip algorithms or sector erase time outs. DQ6 toggles when CE or OE toggles, or an Erase Resume command is invoked. DQ6 is valid after the rising edge of the fourth pulse of WE during programming; after the rising edge of the sixth WE pulse during chip erase; after the last rising edge of the sector erase WE pulse for sector erase. For protected sectors, DQ6 toggles for <1 s during program mode writes, and <5 s during erase (if all selected sectors are protected). Indicates unsuccessful completion of program/erase operation (DQ5 = 1). DATA polling remains active. If DQ5 = 1 during chip erase, all or some sectors are defective; during byte programming or sector erase, the sector is defective (in this case, reset the device and execute a program or erase command sequence to continue working with functional sectors). Attempting to program 0 to 1 will set DQ5 = 1. Checks whether sector erase timer window is open. If DQ3 = 1, erase is in progress; no commands will be accepted. If DQ3 = 0, the device will accept sector erase commands. Check DQ3 before and after each Sector Erase command to verify that the command was accepted. During sector erase, DQ2 toggles with OE or CE only during an attempt to read a sector being erased. During chip erase, DQ2 toggles with OE or CE for all addresses. If DQ5 = 1, DQ2 toggles only at sector addresses where failure occurred, and will not toggle at other sector addresses. Use DQ2 in conjunction with DQ6 to determine whether device is in auto erase or erase suspend mode. RY/BY indicates whether an automated on-chip algorithm is in progress (RY/BY = low) or completed (RY/BY = high). The device does not accept Program/Erase commands when RY/BY = low. RY/BY= high when device is in erase suspend mode. RY/BY = high when device exceeds time limit, indicating that a program or erase operation has failed. RY/BY is an open drain output, enabling multiple RY/BY pins to be tied in parallel with a pull up resistor to VCC. Toggle bit 1 (DQ6) Exceeding time limit (DQ5) Sector erase timer (DQ3) Toggle bit 2 (DQ2) Ready/Busy :ULWH RSHUDWLRQ VWDWXV Status Standard mode Auto programming Program/erase in auto erase Read erasing sector Erase suspend mode Read non-erasing sector Program in erase suspend Auto programming (byte) Exceeded time limits Program/erase in auto erase Program in erase suspend (non-erase suspended sector) DQ2 toggles when an erase-suspended sector is read repeatedly. DQ6 toggles when any address is read repeatedly. DQ2 = 1 if byte address being programmed is read during erase-suspend program mode. DQ7 DQ7 0 1 Data DQ7 DQ7 0 DQ7 DQ6 Toggle Toggle No toggle Data Toggle Toggle Toggle Toggle DQ5 0 0 0 Data 0 1 1 1 DQ3 N/A 1 N/A Data N/A N/A N/A N/A DQ2 No toggle Toggle Toggle Data Toggle Toggle RY/BY 0 0 1 1 0 1 1 1 No toggle No toggle DQ2 toggles when the read address applied points to a sector which is undergoing erase, suspended erase, or a failure to erase. 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 14 of 29 $6/9 6HFWRU SURWHFW DOJRULWKP START PLSCNT = 1 RESET# = VID Wait 1 s 6HFWRU XQSURWHFW DOJRULWKP START PLSCNT = 1 RESET# = VID Wait 1 s Temporary sector unprotect mode No First Write Cycle=60h? Yes Set up sector address Sector protect: write 60h to sector address with A6=0, A1=1, A0=0 Wait 150 s Verify sector protect; write 40h to sector address with A6=0, A1=1, A0=0 Read from sector address with A6=0, A1=1, A0=0 Protect all sectors: The shaded portion of the sector protct algorithm must be initiated for all unprotected sectors before calling the sector unprotect First Write Cycle=60h? Yes No All sectors protected? Yes Sector unprotect: write 60h to sector address with A6=1, A1=1, A0=0 Wait 15 ms Set up first sector address Verify sector unprotect; write 40h to sector address with A6=1, A1=1, A0=0 Read from sector address with A6=1, A1=1, A0=0 No Temporary sector unprotect mode Increment PLSCNT No No Increment PLSCNT PLSCNT=25? Data=01h? No Yes Yes Protect another sector? No Remove VID from RESET# Write reset command Sector protect complete Yes PLSCNT =1000? No Data=00h? Yes Yes Last sector verified? Yes Remove VID from RESET# Write reset command Sector unprotect complete No Set up next sector address Device failed Device failed 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 15 of 29 $6/9 $XWRPDWHG RQFKLS SURJUDPPLQJ DOJRULWKP START $XWRPDWHG RQFKLS HUDVH DOJRULWKP START Write erase command sequence (see below) Write program command sequence (see below) DATA polling or toggle bit successfully completed DATA polling or toggle bit successfully completed Erase complete Increment address Last address? NO Chip erase command sequence x16 mode (address/data): 555h/AAh erase command sequence x16 mode (address/data): 555h/AAh Individual sector/multiple sector YES Programming completed 2AAh/55h 2AAh/55h 555h/80h 555h/80h Program command sequence x16 mode (address/data): 555h/AAh 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h 555h/A0h 2AAh/55h Sector address/30h Sector address/30h Program address/program data Sector address/30h optional sector erase commands The system software should check the status of DQ3 prior to and following each subsequent sector erase command to ensure command completion. The device may not have accepted the command if DQ3 is high on second status check. 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 16 of 29 $6/9 3URJUDPPLQJ XVLQJ XQORFN E\SDVV FRPPDQG START Unlock bypass command sequence x16 mode (address/data) 555h/AAh Write unlock bypass command (3 cycles) 2AAh/55h 555h/20h Write unlock bypass program command (2 cycles) Unlock bypass program command sequence x16 mode (address/data) DATA polling or toggle bit successfully completed Increment address Last address? NO xxxh/A0h program address/ program data Unlock bypass reset command sequence x16 mode (address/data) YES xxxh/90h Write unlock bypass reset command (2 cycles) xxxh/00h Programming completed 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 17 of 29 $6/9 '$7$ SROOLQJ DOJRULWKP Read byte (DQ0-DQ7) Address = VA DQ7 = data ? NO NO DQ5 = 1 ? YES YES DONE Read byte (DQ0-DQ7) Address = VA DQ7 = data ? NO FAIL YES DONE VA = Byte address for programming. VA = any of the sector addresses within the sector being erased during Sector Erase. VA = valid address equals any non-protected sector group address during Chip Erase. DQ7 rechecked even if DQ5 = 1 because DQ5 and DQ7 may not change simultaneously. 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 18 of 29 $6/9 7RJJOH ELW DOJRULWKP Read byte (DQ0-DQ7) Address = don't care DQ6 = toggle ? YES NO DQ5 NO DONE = 1 ? YES Read byte (DQ0-DQ7) Address = don't care DQ6 = toggle ? YES FAIL NO DONE DQ6 rechecked even if DQ5 = 1 because DQ6 may stop toggling when DQ5 changes to 1. 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 19 of 29 $6/9 '& HOHFWULFDO FKDUDFWHULVWLFV Parameter Input load current A9 Input load current Output leakage current Active current, read @ 5MHz Active current, program/erase Automatic sleep mode1 Standby current Deep power down current3 Input low voltage Input high voltage Output low voltage Output high voltage Low VCC lock out voltage Input HV select voltage Symbol Test conditions ILI ILIT ILO ICC1 ICC2 ICC3 ISB IPD VIL VIH VOL VOH VLKO VID IOL = 4.0mA, VCC = VCC MIN IOH = -2.0 mA, VCC = VCC MIN VIN = VSS to VCC, VCC = VCC MAX VCC = VCC MAX, A9 = 10V VOUT = VSS to VCC, VCC = VCC MAX CE = VIL, OE = VIH CE = VIL, OE = VIH CE = VIL, OE = VIH; VIL= 0.3V, VIH = VCC - 0.3V CE = VCC - 0.3V, RESET = VCC - .3V RESET = 0.3V -0.5 0.7xVCC 0.85xVCC 1.5 9 Min - 9&& Max 1 35 1 20 30 5 5 5 0.8 9 Unit A A A mA mA A A A V V V V V V VCC + 0.3 0.45 11 1 Automatic sleep mode enables the deep power down mode when addresses are stable for 150 ns. Typical sleep mode current is 200 nA. 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 20 of 29 $6/9 $& SDUDPHWHUV UHDG F\FOH JEDEC Symbol tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX Std Symbol Parameter tRC tACC tCE tOE tOES tDF tDF tOH Read cycle time Address to output delay Chip enable to output Output enable to output Output enable setup time Chip enable to output High Z Output enable to output High Z Output hold time from addresses, first occurrence of CE or OE Output enable hold time: Read tOEH tPHQV tRH tREADY tRP Output enable hold time: Toggle and data polling RESET high to output delay RESET pin low to read mode RESET pulse -70 Min 70 0 0 10 10 500 Max 70 70 30 25 25 50 10 Min 80 0 0 10 10 500 -80 Max 80 80 30 25 25 50 10 Min 90 0 0 10 10 500 -90 Max 90 90 35 30 30 50 10 -120 Min 120 0 0 10 10 500 Max 120 120 50 30 30 50 10 Unit ns ns ns ns ns ns ns ns ns ns ns s ns 5HDG ZDYHIRUP tRC Addresses Addresses stable tACC CE tDF tOE OE tOEH WE tCE Outputs High Z tRH RESET tOH Output valid High Z tOES 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 21 of 29 $6/9 $& SDUDPHWHUV ZULWH F\FOH JEDEC Symbol tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL Std Symbol tWC tAS tAH tDS tDH tGHWL tCS tCH tWP tWPH -70 Parameter Write cycle time Address setup time Address hold time Data setup time Data hold time Read recover time before write Min 70 0 45 35 0 0 0 0 35 30 Max Min 80 0 45 35 0 0 0 0 35 30 -80 Max Min 90 0 45 45 0 0 0 0 35 30 -90 Max Min 120 0 50 50 0 0 0 0 50 30 -120 :( FRQWUROOHG Max Unit ns ns ns ns ns ns ns ns ns ns CE setup time CE hold time Write pulse width Write pulse width high :ULWH ZDYHIRUP 3rd bus cycle :( FRQWUROOHG tWC tAS Program address DATA polling Program address Addresses 555h tCH tAH CE tGHWL; tOES OE tWP WE tCS tWPH tDH DATA A0h tDS Program data DQ7 DOUT tWHWH1 or 2 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 22 of 29 $6/9 $& SDUDPHWHUV ZULWH F\FOH JEDEC Symbol tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL Std Symbol tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH -70 Parameter Write cycle time Address setup time Address hold time Data setup time Data hold time Read recover time before write WE setup time WE hold time CE pulse width CE pulse width high Min 70 0 45 35 0 0 0 0 35 30 Max Min 80 0 45 35 0 0 0 0 35 30 -80 Max Min 90 0 45 45 0 0 0 0 35 30 -90 Max Min 120 0 50 50 0 0 0 0 50 30 -120 &( FRQWUROOHG Max Unit ns ns ns ns ns ns ns ns ns ns :ULWH ZDYHIRUP DATA polling Addresses 555h tWC WE tGHEL, tOES OE tCP CE tCPH tDH DATA A0h tDS Program data DQ7 DOUT tWHWH1 or 2 Program address tAS tAH Program address &( FRQWUROOHG 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 23 of 29 $6/9 $& SDUDPHWHUV WHPSRUDU\ VHFWRU XQSURWHFW JEDEC Symbol -70/80/90/120 Std Symbol tVIDR tRSP Parameter VID rise and fall time Min 500 4 Max Unit ns s RESET setup time for temporary sector unprotect 7HPSRUDU\ VHFWRU XQSURWHFW ZDYHIRUP RESET CE WE tRSP 12V 0 or 3V tVIDR Program/erase command sequence tVIDR 0 or 3V RY/BY $& SDUDPHWHUV 5(6(7 -70/80/90/120 JEDEC Symbol Std Symbol tRP tRH tREADY Parameter Min 500 50 - Max 20 Unit ns ns s RESET pulse RESET High time before Read RESET Low to Read mode 5(6(7 ZDYHIRUP RESET RY/BY DQ status tRP tREADY tRH status valid data valid data tRP (UDVH ZDYHIRUP Addresses CE tGHWL OE tWP WE tCS Data tDS AAh tWPH tDH 55h 80h AAh 55h tWC i PRGH tWC 555h tAS 2AAh 555h 555h 2AAh Sector address tAH 10h for Chip Erase 30h 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 24 of 29 $6/9 $& 3DUDPHWHUV 5($'<%86< -70/80/90/120 JEDEC Symbol - Std Symbol tVCS tRB tBUSY Parameter VCC setup time Min 50 0 90 Max - Unit s ns ns Recovery time from RY/BY Program/erase valid to RY/BY delay 5<%< ZDYHIRUP CE Rising edge of last WE signal WE Program/erase operation RY/BY VCC tri-stated open-drain tBUSY tRB tVCS '$7$ SROOLQJ ZDYHIRUP CE tCH tOE OE tOEH WE tCE tOH DQ7 Input DQ7 Output DQ7 Output High Z tDF tWHWH1 or 2 7RJJOH ELW ZDYHIRUP CE tOEH WE OE DQ6 tDH tOE toggle toggle no toggle 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 25 of 29 $6/9 :RUGE\WH FRQILJXUDWLRQ JEDEC Symbol -70/80/90/120 Std Symbol tELFL/tELFH tFLQZ tFHQZ Parameter Min 80 Max 10 30 Unit ns ns ns CE to BYTE switching Low or High BYTE switching Low to output High-Z BYTE switching High to output Active %<7( UHDG ZDYHIRUP CE OE BYTE Word to Byte tELFL DQ0-DQ14 DQ15/A-1 BYTE tELFH DQ0-DQ14 Data output DQ15 output tFLQZ DQ0-DQ7 Data output Address input Byte to Word DQ0-DQ14 DQ15/A-1 DQ0-DQ7 Data output Address input tFHQV DQ0-DQ14 Data output DQ15 output %<7( ZULWH ZDYHIRUP CE WE BYTE See Erase/Program operations table for tAS and tAH specifications. tSET (tAS) tHOLD (tAH) falling edge of last WE signal 6HFWRU SURWHFWXQSURWHFW RESET# SA, A6, A1, A0 DATA 1 s VID VIH Don't care Valid* Don't care Valid* Verify 40h Don't care Valid* Sector protect/unprotect 60h 60h Don't care Sector protect: 100 s Sector unprotect: 10 ms Don't care Status CE# WE# OE# * For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0. 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 26 of 29 $6/9 $& WHVW FRQGLWLRQV 1 RU HTXLYDOHQW 'HYLFH XQGHU WHVW &/ . 9 . 1 RU HTXLYDOHQW 966 966 966 7HVW VSHFLILFDWLRQV IRU $& SDUDPHWHUV Test Condition Output Load Output Load Capacitance CL (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 30 5 0.0-3.0 1.5 1.5 -70, -80 -90, -120 1 TTL gate 100 Unit pF ns V V V (UDVH DQG SURJUDPPLQJ SHUIRUPDQFH Limits Parameter Sector erase and verify-1 time (excludes 00h programming prior to erase) Programming time Chip programming time Erase/program cycles 1 Min Typical 1.0 10 15 7.2 100,000 Max 15 300 360 27 - Unit sec s s sec cycles Byte Word - 1 Erase/program cycle test is not verified on each shipped unit. /DWFKXS WROHUDQFH Parameter Input voltage with respect to VSS on A9, OE, and RESET pin Input voltage with respect to VSS on all DQ, address, and control pins Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. Min -1.0 -0.5 -100 Max +12.0 Unit V V mA VCC+0.5 +100 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 27 of 29 $6/9 5HFRPPHQGHG RSHUDWLQJ FRQGLWLRQV Parameter Supply voltage Input voltage Symbol Vcc VSS VIH VIL Min +2.7 0 1.9 -0.5 Max +3.6 0 VCC + 0.3 0.8 Unit V V V V $EVROXWH PD[LPXP UDWLQJV Parameter Input voltage (Input or DQ pin) Input voltage (A9 pin, OE, RESET) Power supply voltage Operating temperature Storage temperature (plastic) Symbol VIN VIN VCC TOPR TSTG Min -0.5 -0.5 -0.5 -55 -65 Max VCC+ 0.5 +12.5 +4.0 +125 +150 Unit V V V C C 150 mA Short circuit output current IOUT Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 7623 SLQ FDSDFLWDQFH Symbol CIN COUT CIN2 Parameter Input capacitance Output capacitance Control pin capacitance Test setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 8 Max 7.5 12 10 Unit pF pF pF 62 SLQ FDSDFLWDQFH DYDLODELOLW\ 7%' Symbol CIN COUT CIN2 Parameter Input capacitance Output capacitance Control pin capacitance Test setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 8 Max 7.5 12 10 Unit pF pF pF 'DWD UHWHQWLRQ Parameter Minimum pattern data retention time Temp.(C) 150 125 Min 10 20 Unit years years 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 28 of 29 $6/9 3DFNDJH GLPHQVLRQV 7KLQ VPDOO RXWOLQH SDFNDJH 7623, c L pin 1 A2 pin 48 A A1 b e 48-pin 12x20 A A1 A2 b c D e E Hd L Min Max - 1.27 0.05 0.15 0.95 1.05 0.17 0.27 0.15 nominal 18.20 18.60 0.50 nominal 11.90 12.10 19.80 20.20 0.50 0.70 0 5 D Hd pin 24 48-pin pin 25 E 3DFNDJH GLPHQVLRQV 6PDOO 2XWOLQH 3ODVWLF 62 DYDLODELOLW\ 7%' 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 c JEDEC MO - 175 AA 44-pin SO Min (mm) Max (mm) 3.1 - 2.9 0.45 SO e He A A1 A2 - 0.05 2.5 0.25 0.09 28.0 12.4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 0-10 b c d e d A2 A1 b E 0.25 28.4 12.8 A l E He l 1.27 (typical) 16.05 (typical) 0.73 1.3 8/30/01; V.0.9.5 $OOLDQFH 6HPLFRQGXFWRU P. 29 of 29 (c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. |
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